1. Field of the Invention
This invention relates to electrically erasable programmable read-only memory (EEPROM) cells.
2. Description of the Prior Art
With conventional split gate flash EEPROM cells a problem exists with the write-erase endurance. In a conventional prior art split gate cell, the floating gate is charged with electrons by channel hot-electron programming and the floating gate is discharged by Fowler-Nordheim tunneling of electrons from the floating gate to the overlap area where the floating gate extends above the drain region. The floating gate is separated from the substrate surface and the drain region by gate oxide, and electrons are trapped in the gate oxide during both the program and erase functions. These trapped electrons produce an electric field which tends to inhibit the floating gate from being charged in the next program cycle since the electrons trapped in the oxide repel those which are being attracted to the floating gate in the next program cycle.
A typical prior art split gate flash EEPROM cell has been described in an article entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology," by Gheorghe Samachisa et al., which appeared in the IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987.
FIGS. 1 and 2 illustrate in simplified and greatly enlarged fashion a typical prior art split gate EEPROM such as that described in the above referenced article. Referring to FIG. 1, a single cell 1 of an EEPROM is shown in top plan view, which cell 1 includes floating gate 2 indicated by dashed lines and control gate 3 which is situated above floating gate 2. Also illustrated in FIG. 1 is drain contact 4. A cross section along lines A--A of FIG. 1 is illustrated in FIG. 2. Referring to FIG. 2, cell 1 is comprised of substrate 5 of semiconductor material having a P-type dopant. Formed in substrate 5 from the upper surface 6 is a drain region 7 of highly doped N-type material and a source region 8 also of highly N-doped material. Channel 9 extends between adjacent edges of source region 8 and drain region 7. Surface 6 of substrate 5 includes a first layer of insulating material 10, which may typically be silicon dioxide, insulating layer 10 forming what is known in the art as the gate oxide. As will be appreciated by reference to FIG. 2, floating gate 2 rests on gate oxide 10 and has one edge overlapping a portion of drain region 7. Formed over floating gate 2 and surface of select transistor channel region is a second insulating material 11 which would typically also be composed of silicon dioxide. Control gate 3 is positioned above channel 9, rests on second insulating layer 11 and has one edge which overlaps a portion of source region 8 and a second edge which extends above floating gate 2, with the overlying edge of control gate 3 generally being aligned with the rightmost edge of floating gate 2. Although not shown in FIG. 2 because of the way the cross section has been taken, field oxide 12 is provided on surface 6 and is indicated in FIG. 1 by the partial crosshatching of its exterior edges. It will be appreciated by reference to FIG. 1 that between the opposite edges of field oxide 12, floating gate 2 extends closely to surface 6 and accordingly overlies drain region 7 between the outer edges of field oxide 12. Similarly, control gate 3 follows the same contour and is positioned more closely to surface 6 between the edges of field oxide 12 above channel region 9.
In programming cell 1, source region 8 is grounded and a programming voltage V.sub.pp of approximately 12 to 13 volts is applied to control gate 3 and a drain voltage V.sub.d of approximately 10 volts is applied to drain region 7. Under these conditions, programming is accomplished by injection of hot-electron from the channel through gate oxide layer in response to a high applied drain voltage as shown in FIG. 2. This manner of programming is known in the art as channel hot-electron programming. To erase cell 1, control gate 3 is grounded and an erase voltage of approximately 15 or 16 volts is applied to drain region 7 and source region 8 is set to float. Under these conditions, electrons travel from floating gate 2 to drain region 7 by tunneling through gate oxide 10 via the path indicated by the arrow extending from floating gate 2 to drain region 7, thereby discharging floating gate 2. In this program/erase cycle, electrons are trapped in gate oxide 10 in the region where floating gate 2 overlaps drain region 7 and this produces the aforementioned deficiency in subsequent programming of cell 1. Also, discharge of floating gate 2 occurs along the length of floating gate 2 between the opposite edges of field oxide 12 above said drain region 7 and accordingly electrons become trapped in the entire overlap between floating gate 2 and drain region 7. Also, it will be appreciated that the paths for the electrons during programming and during erase coincide since current flow is to drain contact 4 which is centered on the opposite side of channel 9 from source region 8. The electrons trapped in gate oxide 10 create a repulsive electric field so that during hot electron programming additional time is required to bring floating gate 2 to the required charge level and hence programming efficiency, as well as the program/erase endurance, are both degraded.
Prior art stacked gate flash-erase EEPROM cells, such as the one described in an article entitled "A FLASH-ERASE EEPROM CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTURE" by H. Kume et al. which appeared in the IEEE Technical Digest of IEDM 1987, pages 560-563, consists of a single floating gate transistor. In this type of cell, programming is achieved by hot-electron injection at the drain edge of the floating gate and erasure by Fowler-Nordheim tunneling of electrons from the floating gate to the source. Although this achieves separation of program and erase paths, charge trapping at the drain side of the floating gate transistor is responsible for threshold voltage (V.sub.t) window closure during write/erase cycling. In addition, source erase without a select transistor will cause a false reading of the cell if the floating gate transistor's threshold voltage (V.sub.t) goes negative. Also, as pointed out above, drain erase presents an endurance issue.
Another example of a stacked gate, flash erase single transistor EEPROM cell (which is programmed and erased in the same fashion as the immediately preceding cell) is described in an article entitled "A SINGLE TRANSISTOR EEPROM CELL AND ITS IMPLEMENTATION IN A 512K CMOS EEPROM" by Satyen Mukherjee et al., which appeared in the IEEE Technical Digest of IEDM 1985, pages 616-619. The cell described in this article shares the same shortcomings as those of the device described in the immediately preceding article.